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applications process control data acquisition systems closed-loop servo-control pc peripherals portable instrumentation programmable attenuation low-power, rail-to-rail output, 12-bit serial input digital-to-analog converter description the dac7513 is a low-power, single, 12-bit buffered voltage output digital-to-analog connector (dac). the on-chip preci- sion output amplifier allows rail-to-rail output swing to be achieved. the dac7513 uses a versatile 3-wire serial inter- face that operates at clock rates up to 30mhz and is compat- ible with standard spi ? , qspi ? , microwire ? , and dsp inter- faces. the dac7513 requires an external reference voltage to set the output range of the dac, this allows the dac7513 to be used in a multiplying mode. the dac7513 incorporates a power-on reset circuit which ensures that the dac output powers up at 0v and remains there until a valid write takes place to the device. the dac7513 contains a power-down feature, accessed over the serial interface, that reduces the current consumption of the device to 200na at 5v. the low-power consumption of this part in normal operation makes it ideally suited to portable battery-operated equip- ment. the power consumption is 0.5mw at 5v reducing to 1 w in power-down mode. the dac7513 is available in an sot23-8 package and an msop-8 package. dac7513 features micro power operation: 115 a at 5v power-on reset to zero power supply: +2.7v to +5.5v ensured monotonic by design settling time: 10 s to 1lsb low-power serial interface with schmitt-triggered inputs on-chip output buffer amplifier, rail-to-rail operation sync interrupt facility sot23-8 and msop-8 packages shift register 12 dac register 12 12-bit dac ref (+) power-down control logic resistor network v dd gnd v out v fb sync v ref clk d in spi and qspi are registered trademarks of motorola. microwire is a registered trademark of national semiconductor. dac7513 sbas157a C october 2000 C revised march 2003 www.ti.com production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ? 2000, 2003 texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
dac7513 2 sbas157a www.ti.com v dd to gnd ........................................................................... C 0.3v to +6v digital input voltage to gnd ................................. C 0.3v to +v dd + 0.3v v out to gnd .......................................................... C 0.3v to +v dd + 0.3v operating temperature range ...................................... C 40 c to +105 c storage temperature range ......................................... C 65 c to +150 c junction temperature range (t j max) ........................................ +150 c sot23 package: power dissipation .................................................... (t j max C t a )/ ja ja thermal impedance ......................................................... 240 c/w lead temperature, soldering: vapor phase (60s) ............................................................... +215 c infrared (15s) ........................................................................ +220 c msop package: power dissipation .......................................................... (t j max C t a )/ ja ja thermal impedance ......................................................... 206 c/w jc thermal impedance .......................................................... 44 c/w lead temperature, soldering: vapor phase (60s) ............................................................... +215 c infrared (15s) ........................................................................ +220 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. absolute maximum ratings (1) pin configurations package/ordering information minimum relative differential specification accuracy nonlinearity package temperature package ordering transport product (lsb) (lsb) package-lead designator (1) range marking number media, quantity dac7513e 8 1 msop-8 dgk C 40 c to +105 c d13e dac7513e/250 tape and reel, 250 """" """ dac7513e/2k5 tape and reel, 2500 dac7513n 8 1 sot23-8 dcn C 40 c to +105 c d13n dac7513n/250 tape and reel, 250 """" """ dac7513n/3k tape and reel, 3000 note: (1) for the most current specifications and package information, refer to our web site at www.ti.com. top view sot23-8 msop-8 v out v fb v ref v dd sync sclk d in gnd 1 2 3 4 8 7 6 5 dac7513 v dd v ref v fb v out gnd d in sclk sync 1 2 3 4 8 7 6 5 dac7513 electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
dac7513 3 sbas157a www.ti.com msop-8 sot23-8 name description 14v dd power supply input, +2.7v to +5.5v 23v ref reference voltage input 32v fb feedback connection for the output amplifier. 41v out analog output voltage from dac. the output amplifier has rail-to-rail operation. 5 8 sync level triggered control input (active low), this is the frame sychronization signal for the input data. when sync goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. the dac is updated following the 16th clock cycle unless sync is taken high before this edge in which case the rising edge of sync acts as an interrupt and the write sequence is ignored by the dac7513. 6 7 sclk serial clock input. data can be transferred at rates up to 30mhz. 76d in serial data input. data is clocked into the 16-bit input shift register on the falling edge of the serial clock input. 8 5 gnd ground reference point for all circuitry on the part. pin descriptions marking artwork top view sot23-8 msop-8 lot trace code pin 1 d13e model code (4 characters max.) ymll grs00035 option 1 pin 1 identifier pin 1 d13n bottom view ymll lot trace code grs00035 option 1
dac7513 4 sbas157a www.ti.com parameter conditions min typ max units static performance (1 ) resolution 12 bits relative accuracy 8lsb differential nonlinearity tested monotonic by design 1lsb zero code error all zeroes loaded to dac register +5 +20 mv full-scale error all ones loaded to dac register C 0.15 C 1.25 % of fsr gain error 1.25 % of fsr zero code error drift C 20 v/ c gain temperature coefficient C 5 ppm of fsr/ c output characteristics (2) output voltage range 0v ref v output voltage settling time 1/4 scale to 3/4 scale change (400 h to c00 h )810 s r l = 2k ? ; 0pf < c l < 200pf r l = 2k ? ; c l = 500pf 12 s slew rate 1v/ s capacitive load stability r l = 470 pf r l = 2k ? 1000 pf code change glitch impulse 1lsb change around major carry 20 nv-s digital feedthrough 0.5 nv-s dc output impedance 1 ? short-circuit current v dd = +5v 50 ma v dd = +3v 20 ma power-up time coming out of power-down mode v dd = +5v 2.5 s coming out of power-down mode v dd = +3v 5 s reference input reference current v ref = v dd = +5v 17 25 a v ref = v dd = +3.6v 12 18 a reference input range 0 v dd v reference input impedance 300 k ? logic inputs (2) input current 1 a v in l, input low voltage v dd = +5v 0.8 v v in l, input low voltage v dd = +3v 0.6 v v in h, input high voltage v dd = +5v 2.4 v v in h, input high voltage v dd = +3v 2.1 v pin capacitance 3pf power requirements v dd 2.7 5.5 v i dd (normal mode) dac active and excluding load current v dd = +3.6v to +5.5v v ih = v dd and v il = gnd 115 170 a v dd = +2.7v to +3.6v v ih = v dd and v il = gnd 100 145 a i dd (all power-down modes) v dd = +3.6v to +5.5v v ih = v dd and v il = gnd 0.2 1 a v dd = +2.7v to +3.6v v ih = v dd and v il = gnd 0.05 1 a power efficiency i out /i dd i load = 2ma, v dd = +5v 93 % temperature range specified performance C 40 +105 c notes: (1) linearity calculated using a reduced code range of 48 to 4047; output unloaded. (2) ensured by design and characteri zation, not production tested. electrical characteristics v dd = +2.7v to +5.5v, r l = 2k ? to gnd, and c l = 200pf to gnd, unless otherwise noted. dac7513e, n
dac7513 5 sbas157a www.ti.com parameter description conditions min typ max units t 1 (3) sclk cycle time v dd = 2.7v to 3.6v 50 ns v dd = 3.6v to 5.5v 33 ns t 2 sclk high time v dd = 2.7v to 3.6v 13 ns v dd = 3.6v to 5.5v 13 ns t 3 sclk low time v dd = 2.7v to 3.6v 22.5 ns v dd = 3.6v to 5.5v 13 ns t 4 sync to sclk rising edge setup time v dd = 2.7v to 3.6v 0 ns v dd = 3.6v to 5.5v 0 ns t 5 data setup time v dd = 2.7v to 3.6v 5 ns v dd = 3.6v to 5.5v 5 ns t 6 data hold time v dd = 2.7v to 3.6v 4.5 ns v dd = 3.6v to 5.5v 4.5 ns t 7 sclk falling edge to sync rising edge v dd = 2.7v to 3.6v 0 ns v dd = 3.6v to 5.5v 0 ns t 8 minimum sync high time v dd = 2.7v to 3.6v 50 ns v dd = 3.6v to 5.5v 33 ns notes: (1) all input signals are specified with t r = t f = 5ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. (2) see serial write operation timing diagram, below. (3) maximum sclk frequency is 30mhz at v dd = +3.6v to +5.5v and 20mhz at v dd = +2.7v to +3.6v. timing characteristics (1, 2) v dd = +2.7v to +5.5v, all specifications C 40 c to +105 c, unless otherwise noted. dac7513e, n serial write operation sclk sync d in db15 db0 t 8 t 3 t 2 t 7 t 4 t 5 t 6 t 1
dac7513 6 sbas157a www.ti.com typical characteristics: v dd = +5v at t a = +25 c and +v dd = +5v, unless otherwise noted. 16.0 12.0 8.0 4.0 0.0 C 4.0 C 8.0 C 12.0 C 16.0 le (lsb) linearity error and differential linearity error vs code ( C 40 c) 0 200 h 400 h 600 h 800 h code a00 h c00 h e00 h fff h 1.0 0.5 0.0 C 0.5 C 1.0 dle (lsb) 16.0 12.0 8.0 4.0 0.0 C 4.0 C 8.0 C 12.0 C 16.0 le (lsb) linearity error and differential linearity error vs code (+25 c) 0 200 h 400 h 600 h 800 h code a00 h c00 h e00 h fff h 1.0 0.5 0.0 C 0.5 C 1.0 dle (lsb) 16.0 12.0 8.0 4.0 0.0 C 4.0 C 8.0 C 12.0 C 16.0 le (lsb) linearity error and differential linearity error vs code (+105 c) 0 200 h 400 h 600 h 800 h code a00 h c00 h e00 h fff h 1.0 0.5 0.0 C 0.5 C 1.0 dle (lsb) typical total unadjusted error 0 tue (lsbs) code 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h 16 8 0 C 8 C 16 zero-scale error vs temperature C 40 error (mv) temperature ( c) 0 40 80 120 30 20 10 0 C 10 C 20 C 30 full-scale error vs temperature C 40 error (mv) temperature ( c) 0 40 80 120 30 20 10 0 C 10 C 20 C 30
dac7513 7 sbas157a www.ti.com typical characteristics: v dd = +5v (cont.) at t a = +25 c and +v dd = +5v, unless otherwise noted. note: all references to i dd include i ref current. i dd histogram frequency i dd ( a) 3000 2500 2000 1500 1000 500 0 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 v ref tied to v dd . source and sink current capability 0 v out (v) i source/sink (ma) 51015 5 4 3 2 1 0 dac loaded with fff h dac loaded with 000 h supply current vs code 0 i dd ( a) code 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h 500 400 300 200 100 0 v ref tied to v dd . supply current vs supply voltage 2.7 i dd ( a) v dd (v) 3.2 3.7 4.2 4.7 5.2 5.7 300 250 200 150 100 50 0 v ref tied to v dd . power-down current vs supply voltage 2.7 i dd (na) v dd (v) 3.2 3.7 4.2 4.7 5.2 5.7 100 90 80 70 60 50 40 30 20 10 0 +25 c C 40 c +105 c supply current vs temperature C 40 i dd ( a) temperature ( c) 0 40 80 120 300 250 200 150 100 50 0 v ref tied to v dd .
dac7513 8 sbas157a www.ti.com typical characteristics: v dd = +5v (cont.) at t a = +25 c and +v dd = +5v, unless otherwise noted. note: all references to i dd include i ref current. supply current vs logic input voltage 0 i dd ( a) v logic (v) 123 45 2500 2000 1500 1000 500 0 full-scale settling time time (1 s/div) clk (5v/div) v out (1v/div) full-scale code change 000 h to fff h output loaded with 2k ? and 200pf to gnd full-scale settling time time (1 s/div) clk (5v/div) v out (1v/div) full-scale code change fff h to 000 h output loaded with 2k ? and 200pf to gnd half-scale settling time time (1 s/div) clk (5v/div) v out (1v/div) half-scale code change 400 h to c00 h output loaded with 2k ? and 200pf to gnd half-scale settling time time (1 s/div) clk (5v/div) v out (1v/div) half-scale code change c00 h to 400 h output loaded with 2k ? and 200pf to gnd power-on reset to 0v time (20 s/div) loaded with 2k ? to v dd . v dd (1v/div) v out (1v/div)
dac7513 9 sbas157a www.ti.com typical characteristics: v dd = +2.7v at t a = +25 c and +v dd = +2.7v, unless otherwise noted. typical characteristics: v dd = +5v (cont.) at t a = +25 c and +v dd = +5v, unless otherwise noted. exiting power-down (800 h loaded) time (5 s/div) clk (5v/div) v out (1v/div) code change glitch time (0.5 s/div) loaded with 2k ? and 200pf to gnd. code change: 800 h to 7ff h . v out (20mv/div) 16.0 12.0 8.0 4.0 0.0 C 4.0 C 8.0 C 12.0 C 16.0 le (lsb) linearity error and differential linearity error vs code ( C 40 c) 0 200 h 400 h 600 h 800 h code a00 h c00 h e00 h fff h 1.0 0.5 0.0 C 0.5 C 1.0 dle (lsb) 16.0 12.0 8.0 4.0 0.0 C 4.0 C 8.0 C 12.0 C 16.0 le (lsb) linearity error and differential linearity error vs code (+25 c) 0 200 h 400 h 600 h 800 h code a00 h c00 h e00 h fff h 1.0 0.5 0.0 C 0.5 C 1.0 dle (lsb) 16.0 12.0 8.0 4.0 0.0 C 4.0 C 8.0 C 12.0 C 16.0 le (lsb) linearity error and differential linearity error vs code (+105 c) 000 h 200 h 400 h 600 h 800 h code a00 h c00 h e00 h fff h 1.0 0.5 0 C 0.5 C 1.0 dle (lsb) typical total unadjusted error 0 tue (lsbs) code 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h 16 8 0 C 8 C 16
dac7513 10 sbas157a www.ti.com zero-scale error vs temperature C 40 error (mv) temperature ( c) 0 40 80 120 30 20 10 0 C 10 C 20 C 30 full-scale error vs temperature C 40 error (mv) temperature ( c) 0 40 80 120 30 20 10 0 C 10 C 20 C 30 typical characteristics: v dd = +2.7v (cont.) at t a = +25 c and +v dd = +2.7v, unless otherwise noted. note: all references to i dd include i ref current. i dd histogram frequency i dd ( a) 3000 2500 2000 1500 1000 500 0 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 v ref tied to v dd . source and sink current capability 0 v out (v) i source/sink (ma) 51015 3 2 1 0 dac loaded with fff h dac loaded with 000 h v dd = +3v 500 400 300 200 100 0 supply current vs code 0 i dd ( a) code 200 h 400 h 600 h 800 h a00 h c00 h e00 h fff h v ref tied to v dd . supply current vs temperature C 40 i dd ( a) temperature ( c) 0 40 80 120 300 250 200 150 100 50 0 v ref tied to v dd .
dac7513 11 sbas157a www.ti.com typical characteristics: v dd = +2.7v (cont.) at t a = +25 c and +v dd = +2.7v, unless otherwise noted. note: all references to i dd include i ref current. supply current vs logic input voltage 0 i dd ( a) v logic (v) 12345 2500 2000 1500 1000 500 0 full-scale settling time time (1 s/div) clk (2.7v/div) v out (1v/div) full-scale code change 000 h to fff h output loaded with 2k ? and 200pf to gnd full-scale settling time time (1 s/div) clk (2.7v/div) v out (1v/div) full-scale code change fff h to 000 h output loaded with 2k ? and 200pf to gnd half-scale settling time time (1 s/div) clk (2.7v/div) v out (1v/div) half-scale code change 400 h to c00 h output loaded with 2k ? and 200pf to gnd half-scale settling time time (1 s/div) clk (2.7v/div) v out (1v/div) half-scale code change c00 h to 400 h output loaded with 2k ? and 200pf to gnd power-on reset to 0v time (20 s/div)
dac7513 12 sbas157a www.ti.com typical characteristics: v dd = +2.7v (cont.) at t a = +25 c and +v dd = +2.7v, unless otherwise noted. exiting power-down (800 h loaded) time (5 s/div) clk (2.7v/div) v out (1v/div) code change glitch time (0.5 s/div) loaded with 2k ? and 200pf to gnd. code change: 800 h to 7ff h . v out (20mv/div) theory of operation dac section the architecture consists of a string dac followed by an output buffer amplifier. figure 1 shows a block diagram of the dac architecture. the input coding to the dac7513 is straight binary, so the ideal output voltage is given by: vv d out ref = ? 4096 where d = decimal equivalent of the binary code that is loaded to the dac register; it can range from 0 to 4095. resistor string the resistor string shown in figure 2 is simply a string of resistors, each of value r. the code loaded into the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. it is ensured monotonic because it is a string of resistors. figure 1. dac7513 architecture. dac register ref (+) resistor string ref ( C ) output amplifier gnd v dd v out v fb output amplifier the output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range of 0v to v dd , it is capable of driving a load of 2k ? in parallel with 1000pf to gnd. the source and sink capabilities of the output amplifier can be seen in the typical characteristics. the slew rate is 1v/ s with a half-scale settling time of 8 s with the output unloaded. figure 2. resistor string. to output amplifier r r r r r (1)
dac7513 13 sbas157a www.ti.com db13 db12 operating mode 0 0 normal operation power-down modes 0 1 output 1k ? to gnd 1 0 output 100k ? to gnd 1 1 high-z the inverting input of the output amplifier is brought out to the v fb pin. this allows for better accuracy in critical applications by tying the v fb point and the amplifier output together directly at the load. other signal conditioning circuitry can also be connected between these points for specific applications. serial interface the dac7513 has a 3-wire serial interface sync , sclk, and d in , which is compatible with spi, qspi, and microwire interface standards as well as most digital signal processors (dsps). see the serial write operation timing diagram for an example of a typical write sequence. the write sequence begins by bringing the sync line low, data from the d in line is clocked into the 16-bit shift register on the falling edge of sclk. the serial clock frequency can be as high as 30mhz, making the dac7513 compatible with high-speed dsps. on the 16th falling edge of the serial clock, the last data bit is clocked in and the programmed function is executed (i.e., a change in the dac register contents and/or a change in the mode of operation). at this point, the sync line may be kept low or brought high. in either case, it must be brought high for a minimum of 33ns before the next write sequence so that a falling edge of sync can initiate the next write sequence. as the sync buffer draws more current when the sync signal is high than it does when it is low, sync must be idled low between write sequences for lowest power operation of the part. as mentioned above, however, it must be brought high again just before the next write sequence. input shift register the input shift register is 16 bits wide, as shown in figure 3. the first two bits are don t cares . the next two bits (pd1 and pd0) are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes). there is a more complete description of the various modes in the power-down modes section. the next 12 bits are the data bits. these are transferred to the dac register on the 16th falling edge of sclk. x x pd1 pd0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table i. modes of operation for the dac7513. figure 3. data input register. figure 4. sync interrupt facility. db15 db0 clk sync d in invalid write sequence: sync high before 16th falling edge valid write sequence: output updates on the 16th falling edge db15 db0 db15 db0 sync interrupt in a normal write sequence, the sync line is kept low for at least 16 falling edges of sclk and the dac is updated on the 16th falling edge. however, if sync is brought high before the 16th falling edge, this acts as an interrupt to the write sequence. the shift register is reset and the write sequence is seen as invalid. neither an update of the dac register contents or a change in the operating mode occurs, as shown in figure 4. power-on reset the dac7513 contains a power-on reset circuit that controls the output voltage during power-up. upon power up, the dac register is filled with zeros and the output voltage is 0v; it remains there until a valid write sequence is made to the dac. this is useful in applications where it is important to know the state of the output of the dac while it is in the process of powering up. power-down modes the dac7513 contains four separate modes of operation, which are programmable by setting two bits (pd1 and pd0) in the control register. table i shows how the state of the bits corresponds to the mode of operation of the device. when both bits are set to 0, the part works normally with its normal power consumption of 115 a at 5v. however, for the three power-down modes, the supply current falls to 200na at 5v (50na at 3v). not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this has
dac7513 14 sbas157a www.ti.com the advantage that the output impedance of the part is known while the part is in power-down mode. there are three different options: the output is connected internally to gnd through a 1k ? resistor; a 100k ? resistor; or it is left open- circuited (high-z). the output stage is illustrated in figure 5. all linear circuitry is shut down when the power-down mode is activated, however, the contents of the dac register are unaffected when in power-down. the time to exit power-down is typically 2.5 s for v dd = 5v, and 5 s for v dd = 3v, (see the typical chacteristics for more information). figure 5. output stage during power-down. resistor string dac amplifier power-down circuitry resistor network v out v fb microprocessor interfacing dac7513 to 8051 interface figure 6 shows a serial interface between the dac7513 and a typical 8051-type microcontroller. the setup for the inter- face is as follows: txd of the 8051 drives sclk of the dac7513, while rxd drives the serial data line of the part; the sync signal is derived from a bit programmable pin on the port. in this case, port line p3.3 is used. when data is to be transmitted to the dac7513, p3.3 is taken low. the 8051 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, a second write cycle is initiated to transmit the second byte figure 6. dac7513 to 80c51/80l51 interface. figure 7. dac7513 to microwire interface. 80c51/80l51 (1) p3.3 txd rxd dac7513 (1) sync sclk d in note: (1) additional pins omitted for clarity. sync sclk d in microwire tm cs sk so dac7513 (1) note: (1) additional pins omitted for clarity. of data, and p3.3 is taken high following the completion of this cycle. the 8051 outputs the serial data in a format which has the lsb first. the dac7513 requires its data with the msb as the first bit received, thus, the 8051 transmit routine must therefore take this into account and mirror the data as needed. dac7513 to microwire interface figure 7 shows an interface between the dac7513 and any microwire compatible device. serial data is shifted out on the falling edge of the serial clock and is clocked into the dac7513 on the rising edge of the sk signal. dac7513 to 68hc11 interface figure 8 shows a serial interface between the dac7513 and the 68hc11 microcontroller. sck of the 68hc11 drives the sclk of the dac7513, while the mosi output drives the serial data line of the dac. the sync signal is derived from a port line (pc7), similar to what was done for the 8051. the 68hc11 must be configured so that its cpol bit is a 0 and its cpha bit is a 1, this configuration causes data appearing on the mosi output as valid on the falling edge of sck. when data is being transmitted to the dac, the sync line is taken low (pc7). serial data from the 68hc11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. in order to load data to the dac7513, pc7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the dac and pc7 is taken high at the end of this procedure. figure 8. dac7513 to 68hc11 interface. 68hc11 (1) pc7 sck mosi sync sclk d in dac7513 (1) note: (1) additional pins omitted for clarity.
dac7513 15 sbas157a www.ti.com (4) (3) figure 10. bipolar operation with the dac7513. dac7513 v ref v out v fb r 1 10k ? r 2 10k ? 3-wire serial interface v ref 10 f 0.1 f C 5v 5v +5v opa703 applications using ref02 as a power supply for the dac7513 due to the extremely low supply current required by the dac7513, an alternative option is to use a ref02 +5v precision voltage reference to supply the required voltage to the part, as shown in figure 9. this is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5v. the ref02 will output a steady supply voltage for the dac7513; if the ref02 is used, the current it needs to supply to the dac7513 is 132 a. this is with no load on the output of the dac, so when the dac output is loaded, the ref02 also needs to supply the current to the load. the total current required (with a 5k ? load on the dac output) is: 132 a + (5v/ 5k ? ) = 1.13ma the load regulation of the ref02 is typically 0.005%/ma, which results in an error of 285 v for the 1.13ma current drawn from it; this corresponds to a 0.2lsb error. bipolar operation using the dac7513 the dac7513 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in figure 10 which will give an output voltage range of v ref . rail-to-rail operation at the amplifier output is achievable using an opa703 as the output amplifier. the output voltage for any input code can be calculated as follows: vv drr r v r r o ref ref = ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? 4096 12 1 2 1 where d represents the input code in decimal (0 to 4095). with v ref = 5v, r 1 = r 2 = 10k ? : v 10 ? d 4096 C 5v o = ? ? ? ? ? ? this is an output voltage range of 5v with 000 h correspond- ing to a C 5v output and fff h corresponding to a +5v output. similarly, using v ref = 2.5v, 2.5v output voltage raw can be achieved. layout a precision analog component requires careful layout, ad- equate bypassing, and clean, well-regulated power supplies. as the dac7513 offers single-supply operation, it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. the more digital logic present in the design and the higher the switching speed, the more difficult it will be to achieve good perfor- mance from the converter. due to the single ground pin of the dac7513, all return currents, including digital and analog return currents, must flow through the gnd pin, which would, ideally, be connected directly to an analog ground plane. this plane would be separate from the ground connection for the digital compo- nents until they were connected at the power-entry point of the system. figure 9. ref02 as power supply to the dac7513. ref02 dac7513 3-wire serial interface +5v 132 a (i dd + i ref ) v out = 0v to 5v sync sclk d in +15 (2)
dac7513 16 sbas157a www.ti.com the power applied to v dd should be well regulated and low noise. switching power supplies and dc/dc converters will often have high-frequency glitches or spikes riding on the output voltage. in addition, digital components can create similar high-frequency spikes as their internal logic switches states; this noise can easily couple into the dac output voltage through various paths between the power connec- tions and analog output. this is only true for the dac7513 if the power supply is also opted to be used as the source of reference voltage for the dac. as with the gnd connection, v dd should be connected to a +5v power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. in addition, the 1 f to 10 f and 0.1 f bypass capacitors are strongly recommended. in some situ- ations, additional bypassing may be required, such as a 100 f electrolytic capacitor or even a pi filter made up of inductors and capacitors all designed to essentially low- pass filter the +5v supply, removing the high-frequency noise.
dac7513 17 sbas157a www.ti.com package drawings dgk (r-pdso-g8) plastic small-outline package 0,69 0,41 0,25 0,15 nom gage plane 4073329/c 08/01 4,98 0,25 5 3,05 4,78 2,95 8 4 3,05 2,95 1 0,38 1,07 max seating plane 0,65 m 0,08 0 C 6 0,10 0,15 0,05 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion. d. falls within jedec mo-187
dac7513 18 sbas157a www.ti.com package drawings (cont.) dcn (r-pdso-g8) plastic small-outline c 4202106/a 03/01 3,00 2,80 3,00 2,60 1,50 1,75 area 0,28 0,45 0 C 10 0,09 0,20 1,30 0,90 0,10 0,60 index 0,00 0,15 C a C 0,65 0,90 1,45 1,95 ref notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. foot length measured reference to flat foot surface parallel to datum a. d. package outline exclusive of mold flash, metal burr and dambar protrusion/intrusion. e. package outline inclusive of solder plating. f. a visual index feature must be located within the cross-hatched area.
package option addendum www.ti.com 11-apr-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples dac7513e/250 active vssop dgk 8 250 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 105 d13e dac7513e/250g4 active vssop dgk 8 250 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 105 d13e dac7513e/2k5 active vssop dgk 8 2500 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 105 d13e dac7513e/2k5g4 active vssop dgk 8 2500 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 105 d13e dac7513n/250 active sot-23 dcn 8 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 105 d13n dac7513n/250g4 active sot-23 dcn 8 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 105 d13n dac7513n/3k active sot-23 dcn 8 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 105 d13n dac7513n/3kg4 active sot-23 dcn 8 3000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 105 d13n (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature.
package option addendum www.ti.com 11-apr-2013 addendum-page 2 (4) multiple top-side markings will be inside parentheses. only one top-side marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire top-side marking for that device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant dac7513e/250 vssop dgk 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 dac7513n/250 sot-23 dcn 8 250 180.0 8.4 3.2 3.1 1.39 4.0 8.0 q3 dac7513n/3k sot-23 dcn 8 3000 180.0 8.4 3.2 3.1 1.39 4.0 8.0 q3 package materials information www.ti.com 8-apr-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) dac7513e/250 vssop dgk 8 250 210.0 185.0 35.0 dac7513n/250 sot-23 dcn 8 250 210.0 185.0 35.0 dac7513n/3k sot-23 dcn 8 3000 210.0 185.0 35.0 package materials information www.ti.com 8-apr-2013 pack materials-page 2

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